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To obtain a high efficiency PA, it is necessary to ensure that the power dissipated in the active device is minimised and this is achieved by ensuring that the overlapping area between the drain voltage and current waveforms in the time domain is minimised. New forms of harmonic matching networks were designed to ensure that the active device is terminated by the optimum impedances at the gate and drain for maximum efficiency.

Three PAs were designed, one operating at 0. For the 0. As the effect of gate capacitance is small at this frequency, the source matching network was designed to obtain a conjugate match at the fundamental frequency only. At the higher frequency of 2. In the first PA design the load and source matching networks were designed to obtain optimum impedances at the fundamental frequency and second harmonic. For the second PA design, these networks were designed to obtain optimum impedances at the fundamental frequency, and second and third harmonics. The practical results are compared with those obtained by simulation.

The PAE obtained in these works is comparable to that reported in published papers. Based on this research five papers have been published in journals and conferences.

optimise the design of an RF power amplifier for envelope tracking applications. amplifier modes," PhD Thesis, Cardiff University, [8]. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Iowa State University . Literature Survey on Concurrent Dual-Band Power Amplifiers. guided me all the way through my Ph. D. life.

An H-shaped microstrip patch antenna is used in the active integrated antenna AIA design. Since the spectrum is a limited resource, it must be distributed effi- ciently among communication providers. This requires that a very large fraction of the RF spectral power is contained within the allocated bandwidth, which is ac- complished by means of pulse shaping filters which significantly increase envelope variations i. The power amplifier PA —located right before the transmitter antenna—is therefore challenged twice: its output must be linear to comply with spectral mask requirements; but it must also be efficient so that feeding power is not wasted and large heat removal hard- ware is avoided.

There are already a number of solutions to improve the linearity—efficiency tradeoff. They can be roughly classified into two main categories: linearization systems e. The latter are based on controlling operating conditions of the active cells i. Popular forms of these techniques are, for example, envelope elimination and restoration EER , envelope tracking ET and load modulation a special case of which is the Doherty Amplifier [4—8].

There are certain requirements for these radio transmitters that are worth naming: 1. Wireless infrastructure covers a decade of frequency 4 GHz to 40 GHz , so the transmitter technology must be as independent of the carrier frequency as possible. Introduction comes at a cost. The output power for radio infrastructure is rather modest, not significantly above 1 W. Efficient operation is important since it allows small sized radio hardware, but it is not as crucial as for base station amplifiers delivering W.

The aim is to produce commercial products, so cost and reliability are pri- orities. Class-A amplifiers are ideally perfectly linear, assuming an ideal transconduc- tance function. In this way high DC power is provided when the input envelope is at its peak, but low DC power is fed for low envelope amplitudes.

This principle is independent of the carrier frequency, can potentially manage high bandwidths, and provides linearity with a significant improvement in efficiency.

From the implementation point of view the technique is attractive because it can be applied to conventional RF linear amplification topologies by readily substituting the static supply for a dynamic one [11]. There are nonetheless certain issues that must be dealt with carefully when manipulating the bias. It is precisely the need for a different design methodology to apply dynamic biasing to RF power amplifiers that gives rise to this research project. Class-B amplifiers have the property that the DC current varies in proportion to the required output current. Therefore, efficiency in back-off can be enhanced by varying the drain bias voltage according to the envelope power of the input signal [2].

Envelope tracking has been used in several different applications ranging from base station amplifiers [12],[13], to handset amplifiers in mobile telephone units [14]. The simplest way to implement ET would be to use an envelope detector at the input of the PA connected to a linear amplifier—the bias source—that feeds the PA with varying voltage and high current. However, there are some issues in this apparent simplicity that are subject of current research. In addition, depending on the output power expected from the amplifier, the cur- rent demand at the drain of the PA can be high.

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On the other hand, the bandwidth of the envelope is several times the RF bandwidth. Man- ufacturing a source that follows rapid envelope variations and that provides the required current is not trivial. The most common solutions are to use switching supplies based on class-S architectures; vary the voltage in fixed voltage steps; or to combine a switching and a linear amplifier, so that the latter amplifies the highest frequency components that contain less power [10],[7],[16].

A possibility is to digitally filter the drain waveform [17],[18]. The drawback is that memory effects will be introduced into the PA, hence a high-order digital predistortion DPD with memory will be necessary to meet linearity requirements, which increases the implementation cost. This work instead proposes varying the drain voltage as a polynomial function of the input power, making the bandwidth proportional to the order of the polynomial.

How the drain voltage is modulated has also an impact on the performance of the system. For example, Nemati et al. The purpose was to determine the maximum PAE point for each constant output power contour. By joining these points and interpolating they extracted dependences of the drain voltage, input power and input phase on the output power level. Hoversten et al. In this case the maximum PAE curve is extracted and filtered in the drain- voltage—input-envelope-voltage space to avoid inflections that increase bandwidth.

Linearity is further improved by means of an adaptive DPD algorithm. Rautio et al.

Drain voltage proportional to input-envelope. Constant gain. Maximum drain efficiency. The comparison showed that the paths could differ from each other up to 3. The conclusion from the literature is that carefully designed drain modulation can positively impact efficiency, linearity and gain.

This last point is important because gain drops with the input power should be avoided, else a buffer amplifier would have to be added before the PA to obtain the same output power. While it becomes more difficult to find biasing functions for the gate and drain working in synchrony, the gate supply can be modulated at higher bandwidths than the drain with less hardware com- plexity.

That is because the efficiency of the gate converter has a smaller impact on overall system efficiency, since the currents at the gate are small—in field effect transistors FET the gate current is in the order of a few microamperes. It has been theoretically proven that the PAE of a class-A PA driven by a modulated signal can be increased by a factor of 8 by using synchronized continuous gate and drain bias variation [22]. The study considered both synchronized and individual variation of gate and drain bias in continuous and step-like fashion using the ideal and the Saleh model.

For the specific case of the Saleh model with continuous gate and drain variation the class-A and -B biased transistor yielded 3. Though this study is most relevant to demonstrate the improvements that DB can bring, it does not address how the bias should change with the envelope of the input signal. On the other hand, Colantonio et al.

The resistor-capacitor RC network ensures unconditional small-signal stability at all frequencies for the selected bias point, though the loss of the shunt inductors at the input also contributes significantly to stability. Maximize the breakdown voltage. Though feedforward has strong linearization capabilities, it offers only modest overall efficiency, and the need for several loops to compensate for the non-ideal error amplifier increase hardware complexity. A case study of dynamic biasing Table 3. Skip to main content. A case study of dynamic biasing 3. When the back-off k tends to infinity, VG tends to 0; and when there is no back-off i.

The device is modeled as a voltage controlled current source. The knee voltage is taken to be constant and the input and output resistances are considered, together with the gate-source and drain-source capacitances. The simulated results show that the system provides better ACPR for high average RF input power compared to the static case.

The assumption of constant drain-source capacitance and transconductance with bias does certainly not apply to several transistor technologies.

How to Design an RF Power Amplifier: Class A, AB and B

This work presents linearity measures that can be used for memoryless polynomial predis- tortion that aim for minimum distortion at the adjacent and alternate channels. In a dynamic bias system the bias will vary between class-A and -B, while the source and load impedances presented to the transistor are fixed. Unfortunately, some internal parameters of the transistor, such as the drain-source capacitance, are sensitive to bias variations, especially to the gate [25],[18].

The load line will hence change with the bias, and so will the optimum load and source impedances for each bias point along the bias path. The question is how to choose the source and load impedances in addition to the bias functions for the system to provide optimum performance—in terms of output power, efficiency, or linearity—together with a high gain at all input power levels despite the mismatch from bias variation.

The problem therefore becomes a set of five variables without considering har- monic tuning: 1.

Input power to tune the load and source impedances. Source impedance at the fundamental frequency 5. Load impedance at the fundamental frequency The determination of the source and load impedances is addressed in the design of the pHEMT amplifier in Chapter 3. Introduction 1. Chapter 3 theoretically analyzes the implications of biasing as a function of input envelope power instead of input envelope amplitude using an idealized tran- sistor model.

In addition, it presents a comparison of the response of HBT and pHEMT transis- tors to different bias functions, and deepens on the idea of using first and second order polynomials for the bias functions, to be able to control the bandwidth of the signals. The possibility of searching heuristically to find optimal bias trajectories is explored in Chapter 4.

An algorithm is proposed based on representing the bias function search as a constrained optimization theory problem. The derivation of the constraints, and a multi-objective error function, together with measures for linearity and dissipated power is explained.

The linearity measure is different from the classical least squares measure, it aims to minimize third and fifth order distortions. Finally, Chapter 5 introduces a full automatized experimental setup that allows to apply dynamic biasing to different transistor technologies. The manufacturing of the bias supplies was oriented towards providing low dis- tortion with frequency and load variations within an adequate bandwidth 5 MHz , as well as an accurate measurement of the instantaneous current for efficiency cal- culations.

The efficiency of the bias supplies is not addressed in this work, as it is a research problem on its own right [26],[5],[4]. Instead, is set on the concept of vary- ing bias with power to limit the bandwidth of the bias waveforms. Overview, scope and contributions about the different applications and advantages of using dynamic gate biasing, dy- namic drain biasing or both, and the impact on linearity, PAE and output power is presented in Chapter 6, which is rounded up with ideas that hopefully will awaken interest for future research.

Different transistor materials and technolo- gies are reviewed, as well as modern efficiency and linearity enhancement methods. The aim is to highlight the strengths, limitations, and application area of each topic.